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n0712hkim 20060117-s00009 no.a0143-1/28 http://onsemi.com semiconductor components industries, llc, 2013 may, 2013 ver.1.04 lc87f5dc8a overview the lc87f5dc8a is an 8-bit microcom puter that, centered around a cpu running at a minimum bus cycle time of 83.3 ns, integrate on a single chip a number of hardware features such as 128k-byte flash rom (onboard rewritable), 4k-byte ram, onchip debugging function, two sophisticated 16-bit timers/counters (may be divided into 8-bit timers), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, two synchronous sio ports (with automatic block transmission/reception capabilities) ,an asynchronous/synchronous sio port, two uart ports (full duplex), four 12-bit pwm channels, an 8-bit 15-channel ad converter, a high-speed clock counter, a system clock frequency divider, and a 29-source 10-vector interrupt feature. features ? flash rom ? single 5v power supply, on-board writeable ? block erase in 128 byte units ? 131072 8 bits (lc87f5dc8a) ? ram ? 4096 9 bits (lc87f5dc8a) ? bus cycle time ? 83.3ns (12mhz) note: bus cycle time indicates the speed to read rom. ? minimum instruction cycle time (tcyc) ? 250ns (12mhz) ordering number : ENA0143 ordering number : ena1951 ordering number : ENA0143 cmos ic from 128k byte, ram 4096 byte on-chip 8-bit 1-chip microcontroller * this product is licensed from silicon storage technology, inc. (usa).
lc87f5dc8a no.a0143-2/28 ? ports ? normal withstand voltage i/o ports ports whose i/o direction can be designated in 1-bit units 62 (p1n, p2n, p3n, p70 to p73, p8n, pan, pbn, pcn, s2pn, pwm0, pwm1, xt2) ports whose i/o direction can be designated in 4-bit units 8 (p0n) ? normal withstand voltage input port 1 (xt1) ? dedicated oscillator ports 2 (cf1, cf2) ? reset pins 1 (res) ? power pins 8 (v ss 1 to v ss 4, v dd 1 to v dd 4) ? timers ? timer 0: 16-bit timer/counter with capture register mode 0: 8-bit timer with an 8-bit programmable prescaler (with two 8-bit capture registers) 2-channels mode 1: 8-bit timer with an 8-bit programmable prescal er (with two 8-bit capture registers) + 8-bit counter (with two 8-bit capture registers) mode 2: 16-bit timer with an 8-bit programmabl e prescaler (with two 16-bit capture registers) mode 3: 16-bit counter (with 2 16-bit capture registers) ? timer 1: 16-bit timer/counter that support pwm/toggle output mode 0: 8-bit timer with an 8-bit prescaler (with toggle outputs) + 8-bit timer/counter (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2-channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle outputs) ? base timer 1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. 2) interrupts programmable in 5 different time schemes. ? high-speed clock counter ? can count clocks with a maximum clock rate of 20mhz (at a main clock of 10mhz). ? can generate output real-time. ? serial interface ? sio0: 8 bit synchronous serial interface 1) lsb first/msb first mode selectable 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tcyc) 3) automatic continuous data transmission (1 to 256 bits) ? sio1: 8 bit asynchronous/synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8 data bits, 1 stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8 data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8 data bits, stop detect) ? sio2: 8 bit synchronous serial interface 1) lsb first mode 2) built-in 8-bit baudrate generator (maximum transfer clock cycle = 4/3 tcyc) 3) automatic continuous data transmission (1 to 32 bytes)
lc87f5dc8a no.a0143-3/28 ? uart: 2 channels ? full duplex ? 7/8/9 bit data bits selectable ? 1 stop bit (2 bits in continuous transmission mode) ? built-in baudrate generator (with ba udrates of 16/3 to 8192/3 tcyc) ? ad converter: 8 bits 15 channels ? pwm: multifrequency 12-bit pwm 4 channels ? remote control receiver circuit (sharing pins with p73, int3, and t0in) ? noise filtering function (noise filter time constant selectable from 1 tcyc, 32 tcyc, and 128 tcyc) ? the noise filtering function is available for the int3, t0 in, or t0hcp signal at p73. when p73 is read with an instruction, the signal level at that pin is read regardless of the availability of the noise filtering function. ? watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable ? interrupts ? 29 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x)) of multiplex interrupt cont rol. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interr upts of the same level, the interrupt into the smallest vector address takes precedence. no. vector selectable level interrupt signal 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4 4 0001bh h or l int3/int5/base timer 5 00023h h or l t0h/int6 6 0002bh h or l t1l/t1h/int7 7 00033h h or l sio0/uart1 receive/uart2 receive 8 0003bh h or l sio1/sio2/uart1 transmit/uart2 transmit 9 00043h h or l adc/t6/t7/pwm4, pwm5 10 0004bh h or l port 0/t4/t5/pwm0, pwm1 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? subroutine stack levels: 2048 levels maximum (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? oscillation circuits ? rc oscillation circuit (internal): for system clock ? cf oscillation circuit: for system clock, with internal rf ? crystal oscillation circuit: for low-speed system clock ? multifrequency rc oscillation circuit (internal): for system clock
lc87f5dc8a no.a0143-4/28 ? system clock divider function ? can run on low current. ? the minimum instruction cycle selectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz). ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) canceled by a system rese t or occurrence of interrupt ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc, and crystal oscilla tors automatically stop operation. 2) there are three ways of resetting the hold mode. (1) setting the reset pin to the low level. (2) setting at least one of the int0, int1, int2 , int4, and int5 pins to the specified level (3) having an interrupt source established at port 0 ? x'tal hold mode: suspends instruction execution and the op eration of the peripheral circuits except the base timer. 1) the cf and rc oscillators automatically stop operation. 2) the state of crystal oscillation established when the hold mode is entered is retained. 3) there are four ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level. (2) setting at least one of the int0, int1, int2, int4, and int5 pins to the specified level. (3) having an interrupt source established at port 0. (4) having an interrupt source established in the base timer circuit. ? on-chip debugging function ? permits software debugging with the test device installed on the target board. ? shipping form ? qip80e (14 20): lead-free type ? tqfp80j (12 12): lead-free type ? development tools ? evaluation (eva) chip: lc87ev690 ? emulator: eva62s + ecb876600d + sub875d00 + pod80qfp or pod80sqfp ice-b877300 + sub875d00 + pod80qfp or pod80sqfp ? flash rom writer adapter: w87f54256q(qip80e), w87f54256sq(tqfp80)
lc87f5dc8a no.a0143-5/28 package dimensions unit : mm (typ) 3174a package dimensions unit : mm (typ) 3290 sanyo : qip80e(14x20) 20.0 23.2 0.15 0.35 0.8 (2.7) 3.0max 0.1 0.8 (0.8) 24 1 14.0 17.2 25 40 41 64 65 80 120 21 40 41 60 80 61 (1.25) 0.2 0.5 0.125 12.0 12.0 14.0 14.0 0.5 (1.0) 0.1 1.2max sanyo : tqfp80j(12x12)
lc87f5dc8a no.a0143-6/28 pin assignment qip80e (14 20) ?lead-free type? lc87f5dc8a pb5 pb6 pb7 p27/int5/t1in/t0lcp/t0hcp p26/int5/t1in/t0lcp/t0hcp p25/int5/t1in/t0lcp/t0hcp p24/int5/t1in/t0lcp/t0hcp/int7/t0hcp1 p23/int4/t1in/t0lcp/t0hcp/urx2 p22/int4/t1in/t0lcp/t0hcp/utx2 p21/int4/t1in/t0lcp/t0hcp p20/int4/t1in/t0lcp/t0hcp/int6/t0lcp1 p07/t7o p06/t6o p05/cko p04 p03 p02 p01 p00 v ss 2 v dd 2 pwm0 pwm1 si2p3/sck20 si2p2/sck2 si2p1/si2/sb2 si2p0/do2 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 p13/so1 p12/sck0 p11/si0/sb0 p10/so0 p34 p33/urx1 p32/utx1 p31/pwm5 p30/pwm4 pb4 pb3 pb2 pb1 pb0 v ss 3 v dd 3 pc7/dbgp2 pc6/dbgp1 pc5/dbgp0 pc4 pc3 pc2 pc1 pc0 pa0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 pa1 pa2 pa3/an12 pa4/an13 pa5/an14 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/t0lcp p73/int3/t0in/t0hcp res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 p86/an6 p87/an7 top view
lc87f5dc8a no.a0143-7/28 tqfp80j (12 12) ?lead-free type? lc87f5dc8a top view 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 pa3/an12 pa4/an13 pa5/an14 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in/t0lcp p73/int3/t0in/t0hcp res xt1/an10 xt2/an11 v ss 1 cf1 cf2 v dd 1 p80/an0 p81/an1 p82/an2 p83/an3 p84/an4 p85/an5 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 pb7 p27/int5/t1in/t0lcp/t0hcp p26/int5/t1in/t0lcp/t0hcp p25/int5/t1in/t0lcp/t0hcp p24/int5/t1in/t0lcp/t0hcp/int7/t0hcp1 p23/int4/t1in/t0lcp/t0hcp/urx2 p22/int4/t1in/t0lcp/t0hcp/utx2 p21/int4/t1in/t0lcp/t0hcp p20/int4/t1in/t0lcp/t0hcp/int6/t0lcp1 p07/t7o p06/t6o p05/cko p04 p03 p02 p01 p00 v ss 2 v dd 2 pwm0 pwm1 si2p3/sck20 si2p2/sck2 si2p1/si2/sb2 si2p0/so2 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 p13/so1 p12/sck0 p11/si0/sb0 p10/so0 p34 p33/urx1 p32/utx1 p31/pwm5 p30/pwm4 p87/an7 p86/an6 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 pb6 pb5 pb4 pb3 pb2 pb1 pb0 v ss 3 v dd 3 pc7/dbgp2 pc6/dbgp1 pc5/dbgp0 pc4 pc3 pc2 pc1 pc0 pa0 pa1 pa2 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
lc87f5dc8a no.a0143-8/28 qip name tqfp qip name tqfp 1 pa1 79 41 si2p3/sck20 39 2 pa2 80 42 pwm1 40 3 pa3/an12 1 43 pwm0 41 4 pa4/an13 2 44 v dd 2 42 5 pa5/an14 3 45 v ss 2 43 6 p70/int0/t0lcp/an8 4 46 p00 44 7 p71/int1/t0hcp/an9 5 47 p01 45 8 p72/int2/t0in/t0lcp 6 48 p02 46 9 p73/int3/t0in/t0hcp 7 49 p03 47 10 res 8 50 p04 48 11 xt1/an10 9 51 p05/cko 49 12 xt2/an11 10 52 p06/t6o 50 13 v ss 1 11 53 p07/t7o 51 14 cf1 12 54 p20/int4/t1in/t0lcp/t0hcp/ int6/t0lcp1 52 15 cf2 13 55 p21/int4/t1in/t0lcp/t0hcp 53 16 v dd 1 14 56 p22/int4/t1in/t0lcp/t0hcp/ utx2 54 17 p80/an0 15 57 p23/int4/t1in/t0lcp/t0hcp/ urx2 55 18 p81/an1 16 58 p24/int5/t1in/t0lcp/t0hcp/ int7/t0hcp1 56 19 p82/an2 17 59 p25/int5/t1in/t0lcp/t0hcp 57 20 p83/an3 18 60 p26/int5/t1in/t0lcp/t0hcp 58 21 p84/an4 19 61 p27/int5/t1in/t0lcp/t0hcp 59 22 p85/an5 20 62 pb7 60 23 p86/an6 21 63 pb6 61 24 p87/an7 22 64 pb5 62 25 p30/pwm4 23 65 pb4 63 26 p31/pwm5 24 66 pb3 64 27 p32/utx1 25 67 pb2 65 28 p33/urx1 26 68 pb1 66 29 p34 27 69 pb0 67 30 p10/so0 28 70 v ss 3 68 31 p11/si0/sb0 29 71 v dd 3 69 32 p12/sck0 30 72 pc7/dbgp2 70 33 p13/so1 31 73 pc6/dbgp1 71 34 p14/si1/sb1 32 74 pc5/dbgp0 72 35 p15/sck1 33 75 pc4 73 36 p16/t1pwml 34 76 pc3 74 37 p17/t1pwmh/buz 35 77 pc2 75 38 si2p0/so2 36 78 pc1 76 39 si2p1/si2/sb2 37 79 pc0 77 40 si2p2/sck2 38 80 pa0 78
lc87f5dc8a no.a0143-9/28 system block diagram interrupt control standby control ir pla flash rom clock generator cf rc x?tal pc bus interface port 0 port 1 sio0 sio1 sio2 timer 0 timer 1 timer 4 timer 5 port 3 port 7 port 8 adc int0-3 noise rejection filter acc b register c register psw rar ram stack pointer watch dog timer alu pwm0 pwm1 base timer port 2 int4, 5, 6, 7 uart2 pwm4 timer 6 timer 7 mrc port a port b port c uart1 pwm5 on-chip debugger
lc87f5dc8a no.a0143-10/28 pin description name i/o function description option v ss 1 v ss 2 v ss 3 - power supply pin (-) no v dd 1 v dd 2 v dd 3 - power supply pin (+) no port 0 i/o ? 8-bit i/o port ? i/o specifiable in 4-bit units ? pull-up resistors can be turned on and off in 4-bit units ? hold release input ? port 0 interrupt input ? pin functions p05 :system clock output p06 : timer 6 toggle output p07 : timer 7 toggle output yes p00 to p07 port 1 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? pin functions p10 : sio0 data output p11 : sio0 data input, bus i/o p12 : sio0 clock i/o p13 : sio1 data output p14 : sio1 data input, bus i/o p15 : sio1 clock i/o p16 : timer 1pwml output p17 : timer 1pwmh output, beeper output yes p10 to p17 port 2 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? other functions p20 : int4 input/hold reset input/timer 1 event input/timer 0l capture input/ timer 0h capture input/int6 input/timer 0l capture 1 input p21 : int4 input/hold reset input/timer 1 event i nput/timer 0l capture input/timer 0h capture input p22 : int4 input/hold reset input/time r 1 event input/timer 0l capture input/ timer 0h capture input/uart2 transmit p23 : int4 input/hold reset input/timer 1 event input/timer 0l capture input/ timer 0h capture input/uart2 receive p24 : int5 input/hold reset input/timer 1 event input/timer 0l capture input/ timer 0h capture inputint7 i nput/timer 0h capture 1 input p25 to p27 : int5 input/hold re set input/timer 1 event input/tim er0l capture input/timer 0h capture input interrupt acknowledge type interrupt acknowledge type yes p20 to p27 rising falling rising & falling h level l level int4 int5 int6 int7 y y y y y y y y y y y y n n n n n n n n port 3 i/o ? 5-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions p30: pwm4 output p31: pwm5 output p32: uart1 transmit p33: uart1 receive yes p30 to p34 continued on next page.
lc87f5dc8a no.a0143-11/28 continued from preceding page. pin name i/o function description option port 7 i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units ? other functions p70 : int0 input/hold release input/timer 0l capture input/output for watchdog timer p71 : int1 input/hold release input/timer 0h capture input p72 : int2 input/hold release input/timer 0 event input/timer 0l capture input p73 : int3 input with noise filter/timer 0 event input/timer 0h capture input interrupt acknowledge type no p70 to p73 rising falling rising & falling h level l level int0 int1 int2 int3 y y y y y y y y n n y y y y n n y y n n ? ad converter input port : an8 (p70), an9 (p71) port 8 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? other functions p80 to p87: ad converter input port no p80 to p87 port a i/o ? 6-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units yes pa0 to pa5 port b i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units yes pb0 to pb7 port c i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistor can be turned on and off in 1-bit units ? pin functions pc5 to pc7 : on-chip debugger yes pc0 to pc7 sio2 port i/o ? 4-bit i/o port ? i/o specifiable in 1-bit units ? shared functions: si2p0: sio2 data output si2p1: sio2 data input, bus input/output si2p2: sio2 cl ock input/output si2p3: sio2 clock output no si2p0 to si2p3 pwm0 o ? pwm0 output port ? general-purpose i/o available no pwm1 o ? pwm1 output port ? general-purpose i/o available no res i reset pin no xt1 i ? input terminal for 32.768khz x'tal oscillation ? shared functions: an10: ad converter input port general-purpose input port must be connected to v dd1 if not to be used no xt2 i/o ? output terminal for 32.768khz x'tal oscillation ? shared functions: an11: ad converter input port general-purpose i/o port must be set for oscillation and kept open if not to be used no cf1 i ceramic resonator input pin no cf2 o ceramic resonator output pin no
lc87f5dc8a no.a0143-12/28 port output configuration the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. port name option selected in units of option type output type pull-up resistor p00 to p07 1 bit 1 cmos programmable (note 1) 2 n-channel open drain no p10 to p17 p20 to p27 p30 to p34 1 bit 1 cmos programmable 2 n-channel open drain programmable pa0 to pa5 pb0 to pb7 pc0 to pc7 1 bit 1 cmos programmable 2 n-channel open drain programmable p70 - no n-channel open drain programmable p71 to p73 - no cmos programmable p80 to p87 - no n-channel open drain no si2p0, si2ps si2p3 pwm0, pwm1 - no cmos no si2p1 - no cmos (when selected as ordinary port) n-channel open drain (when sio2 data is selected) no xt1 - no input only no xt2 - no output for 32.768khz quartz oscillator n-channel open drain (when in general-purpose output mode) no note 1: programmable pull-up resistors for port 0 are controlled in 4-bit units (p00 to 03, p04 to 07). * 1: make the following connection to minimize the noise input to the vdd1 pin and prolong the backup time. be sure to electrically short the vss1, vss2, and vss3 pins. example 1: when backup is active in the hold mode, the high level of the port outputs is supplied by the backup capacitors. power supply v ss 1 for backup v ss 2 v ss 3 v dd 3 v dd 2 v dd 1 lsi
lc87f5dc8a no.a0143-13/28 example 2: the high-level output at the ports is unstable when the hold mode backup is in effect. absolute maximum ratings at ta = 25c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pins/remarks conditions specification v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 v input voltage vi(1) xt1, cf1 -0.3 v dd +0.3 input/output voltage vio(1) ports 0, 1, 2 ports 3, 7, 8 ports a, b, c si2p0 to si2p3 pwm0, pwm1, xt2 -0.3 v dd +0.3 high level output current peak output current ioph(1) ports 0, 1, 2, 3 ports a, b, c si2p0 to si2p3 cmos output select per 1 application pin -10 ma ioph(2) pwm0, pwm1 per 1 application pin -20 ioph(3) p71 to p73 per 1 application pin -5 average output current (note1-1) iom(1) ports 0, 1, 2, 3 ports a, b, c si2p0 to si2p3 cmos output select per 1 application pin -7.5 iom(2) pwm0, pwm1 per 1 application pin -15 iom(3) p71 to p73 per 1 application pin -3 total output current ioah(1) p71 to p73 total of all applicable pins -10 ioah(2) ports 1, 3 pwm0, pwm1 si2p0 to si2p3 total of all applicable pins -25 ioah(3) ports 0 total of all applicable pins -25 ioah(4) port 0, 1, 3 pwm0, pwm1 si2p0 to si2p3 total of all applicable pins -45 ioah(5) ports 2, b total of all applicable pins -25 ioah(6) ports a, c total of all applicable pins -25 ioah(7) ports 2, a, b, c to tal of all applicable pins -45 note 1-1: average output current is av erage of current in 100ms interval. continued on next page. power supply v ss 1 for backup v ss 2 v ss 3 v dd 3 v dd 2 v dd 1 lsi
lc87f5dc8a no.a0143-14/28 continued from preceding page. parameter symbol pins/remarks conditions specification v dd [v] min typ max unit low level output current peak output current iopl(1) p02-p07 ports 1, 2, 3 ports a, b, c si2p0 to si2p3 pwm0, pwm1 per 1 application pin 20 ma iopl(2) p00, p01 per 1 application pin 30 iopl(3) ports 7, 8, xt2 per 1 application pin 10 average output current (note1-1) ioml(1) p02-p07 ports 1, 2, 3 ports a, b, c si2p0 to si2p3 pwm0, pwm1 per 1 application pin 15 ioml(2) p00, p01 per 1 application pin 20 ioml(3) ports 7, 8, xt2 per 1 application pin 7.5 total output current ioal(1) port 7, xt2 total of all applicable pins 15 ioal(2) port 8 total of all applicable pins 15 ioal(3) ports 7, 8, xt2 total of all applicable pins 20 ioal(4) port 1, 3 pwm0, pwm1 si2p0 to si2p3 total of all applicable pins 45 ioal(5) port 0 total of all applicable pins 45 ioal(6) port 0, 1, 3 pwm0, pwm1 si2p0 to si2p3 total of all applicable pins 80 ioal(7) ports 2, b total of all applicable pins 45 ioal(8) ports a, c total of all applicable pins 45 ioal(9) ports 2, a, b, c total of all applicable pins 80 maximum power consumption pdmax qip80e 368 mw tqfp80j 325 operating temperature range topr -20 70 c storage temperature range tstg -55 125 note 1-1: average output current is av erage of current in 100ms interval. stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended oper ating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliabili ty.
lc87f5dc8a no.a0143-15/28 recommended operating range at ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pins/remarks conditions specification v dd [v] min typ max unit operating supply voltage (note2-1) v dd (1) v dd 1=v dd 2=v dd 3 0.245s tcyc 200s 2.8 5.5 v 0.367s tcyc 200s 2.5 5.5 1.47s tcyc 200s 2.2 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents in hold mode. 2.0 5.5 high level input voltage v ih (1) ports 1, 2, 3 si2p0 to si2p3 p71 to p73 p70 port input/ interrupt side 2.2 to 5.5 0.3v dd +0.7 v dd v ih (2) ports 0, 8 ports a, b, c pwm0,pwm1 2.2 to 5.5 0.3v dd +0.7 v dd v ih (3) p70 watchdog timer side 2.2 to 5.5 0.9v dd v dd v ih (4) xt1, xt2, cf1, res 2.2 to 5.5 0.75v dd v dd low level input voltage v il (1) ports 1, 2, 3 si2p0 to si2p3 p71 to p73 p70 port input/ interrupt 2.2 to 5.5 v ss 0.1v dd +0.4 v il (2) 2.2 to 4.0 v ss 0.2v dd v il (3) ports 0, 8 ports a, b, c pwm0,pwm1 4.0 to 5.5 v ss 0.15v dd +0.4 v il (4) 2.2 to 4.0 v ss 0.2v dd v il (5) port 70 watchdog timer 2.2 to 5.5 v ss 0.8v dd -1.0 v il (6) xt1, xt2, cf1, res 2.2 to 5.5 v ss 0.25v dd instruction cycle time tcyc (note2-2) 2.8 to 5.5 0.245 200 s 2.5 to 5.5 0.367 200 2.2 to 5.5 1.470 200 external system clock frequency fexcf(1) cf1 ? cf2 pin open ? system clock frequency division rate = 1/1 ? external system clock duty = 505% 2.8 to 5.5 0.1 12 mhz 2.5 to 5.5 0.1 8 2.2 to 5.5 0.1 2 ? cf2 pin open ? system clock frequency division rate = 1/2 2.8 to 5.5 0.2 24.4 2.5 to 5.5 0.2 16 2.2 to 5.5 0.2 4 oscillation frequency range (note2-3) fmcf(1) cf1, cf2 12mhz ceramic oscillation see fig. 1. 2.8 to 5.5 12 mhz fmcf(2) cf1, cf2 8mhz ceramic oscillation see fig. 1. 2.5 to 5.5 8 fmcf(3) cf1, cf2 4mhz ceramic oscillation see fig. 1. 2.2 to 5.5 4 fmrc internal rc oscillation 2.2 to 5.5 0.3 1.0 2.0 fmmrc frequency variable rc oscillation source oscillation 2.2 to 5.5 16 fsx?tal xt1, xt2 32.768khz crystal oscillation. see fig. 2. 2.2 to 5.5 32.768 khz note 2-1: v dd must be held greater than or equal to 3.0v in the flash rom onboard programming mode. note 2-2: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-3: see tables 1 and 2 for the oscillation constants.
lc87f5dc8a no.a0143-16/28 electrical characteristics at ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high level input current i ih (1) ports 0, 1, 2 ports 3, 7, 8 ports a, b, c si2p0 to si2p3 res pwm0, pwm1 output disable pull-up resistor off v in =v dd (including the off-leak current of the output tr.) 2.2 to 5.5 1 a i ih (2) xt1, xt2 using as an input port v in =v dd 2.2 to 5.5 1 i ih (3) cf1 v in =vdd 2.2 to 5.5 15 low level input current i il (1) ports 0, 1, 2 ports 3, 7, 8 ports a, b, c si2p0 to si2p3 res pwm0, pwm1 output disable pull-up resistor off v in =v ss (including the off-leak current of the output tr.) 2.2 to 5.5 -1 i il (2) xt1, xt2 using as an input port v in =v ss 2.2 to 5.5 -1 i il (3) cf1 v in =v ss 2.2 to 5.5 -15 high level output voltage v oh (1) ports 0, 1, 2, 3 ports a, b, c si2p0 to si2p i oh =-1.0ma 4.5 to 5.5 v dd -1 v v oh (2) i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (3) i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (4) ports 71, 72, 73 i oh =-0.4ma 3.0 to 5.5 v dd -0.4 v oh (5) i oh =-0.2ma 2.2 to 5.5 v dd -0.4 v oh (6) pwm0, pwm1 p30,p31(pwm4,5 output mode) i oh =-10ma 4.5 to 5.5 v dd -1.5 v oh (7) i oh =-1.6ma 3.0 to 5.5 v dd -0.4 v oh (8) i oh =-1.0ma 2.2 to 5.5 v dd -0.4 low level output voltage v ol (1) ports 0, 1, 2, 3 ports a, b, c si2p0 to si2p3 pwm0, pwm1 i ol =10ma 4.5 to 5.5 1.5 v ol (2) i ol =1.6ma 3.0 to 5.5 0.4 v ol (3) i ol =1.0ma 2.2 to 5.5 0.4 v ol (4) p00, p01 i ol =30ma 4.5 to 5.5 1.5 v ol (5) i ol =5.0ma 3.0 to 5.5 0.4 v ol (6) i ol =2.5ma 2.2 to 5.5 0.4 v ol (7) ports 7, 8,xt2 i ol =1.6ma 3.0 to 5.5 0.4 v ol (8) i ol =1.0ma 2.2 to 5.5 0.4 pull-up resistation rpu ports 0, 1, 2, 3 port 7 ports a, b, c v oh =0.9v dd 2.2 to 5.5 15 40 70 k hysteresis voltage vhis res ports 1, 2, 7 si2p0 to si2p3 2.2 to 5.5 0.1v dd v pin capacitance cp all pins ? for pins other than that under test : v in =v ss ? f=1mhz ? ta=25 c 2.2 to 5.5 10 pf
lc87f5dc8a no.a0143-17/28 serial i/o characteristics at ta=-20 to +70 c, v ss 1=v ss 2=v ss 3=0v 1. sio0 serial i/o characteristics (note 4-1-1) parameter symbol pins/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(1) sck0(p12) ? see fig. 6. 2.2 to 5.5 2 tcyc low level pulse width tsckl(1) 1 high level pulse width tsckh(1) 1 tsckha(1a) ? continuous data transmission/reception mode ? sio2 is not in use simultaneous. ? see fig. 6. ? (note 4-1-2) 4 tsckha(1b) ? continuous data transmission/reception mode ? sio2 is in use simultaneous. ? see fig. 6. ? (note 4-1-2) 6 output clock frequency tsck(2) sck0(p12) ? cmos output selected. ? see fig. 6. 2.2 to 5.5 4/3 low level pulse width tsckl(2) 1/2 tsck high level pulse width tsckh(2) 1/2 tsckha(2a) ? continuous data transmission/reception mode ? sio2 is not in use simultaneous. ? cmos output selected. ? see fig. 6. tsckh(2) +2tcyc tsckh(2) + (10/3)tcyc tcyc tsckha(2b) ? continuous data transmission/reception mode ? sio2 is in use simultaneous. ? cmos output selected. ? see fig. 6. tsckh(2) +2tcyc tsckh(2) + (16/3)tcyc serial input data setup time tsdi(1) si0(p11), sb0(p11) ? must be specified with respect to rising edge of sioclk ? see fig. 6. 2.2 to 5.5 0.03 s data hold time thdi(1) 0.03 serial output input clock output delay time tdd0(1) so0(p10), sb0(p11), ? continuous data transmission/reception mode ? (note 4-1-3) 2.2 to 5.5 (1/3)tcyc +0.05 tdd0(2) ? synchronous 8-bit mode. ? (note 4-1-3) 1tcyc +0.05 output clock tdd0(3) ? (note 4-1-3) (1/3)tcyc +0.05 note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: to use serial-clock-input in continuous trans/rec mode, a time from si0run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
lc87f5dc8a no.a0143-18/28 2. sio1 serial i/o char acteristics (note 4-2-1) parameter symbol pins/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(3) sck1(p15) ? see fig. 6. 2.2 to 5.5 2 tcyc low level pulse width tsckl(3) 1 high level pulse width tsckh(3) 1 output clock frequency tsck(4) sck1(p15) ? cmos output selected. ? see fig. 6. 2.2 to 5.5 2 low level pulse width tsckl(4) 1/2 tsck high level pulse width tsckh(4) 1/2 serial input data setup time tsdi(2) si1(p14), sb1(p14) ? must be specified with respect to rising edge of sioclk ? see fig. 6. 2.2 to 5.5 0.03 s data hold time thdi(2) 0.03 serial output output delay time tdd0(4) so1(p13), sb1(p14) ? must be specified with respect to falling edge of sioclk ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.2 to 5.5 (1/3)tcyc +0.05 note 4-2-1: these specifications are theoretical values. add margin depending on its use.
lc87f5dc8a no.a0143-19/28 3. sio2 serial i/o char acteristics (note 4-3-1) parameter symbol pins/ remarks conditions specification v dd [v] min typ max unit serial clock input clock frequency tsck(5) sck2 (si2p2) ? see fig. 6. 2.2 to 5.5 2 tcyc low level pulse width tsckl(5) 1 high level pulse width tsckh(5) 1 tsckha(5a) ? continuous data transmission/ reception mode of sio0 is not in use simultaneous. ? see fig. 6. ? (note 4-3-2) 4 tsckha(5b) ? continuous data transmission/ reception mode of sio0 is in use simultaneous. ? see fig. 6. ? (note 4-3-2) 7 output clock frequency tsck(6) sck2 (si2p2), sck2o (si2p3) ? cmos output selected. ? see fig. 6. 2.2 to 5.5 4/3 low level pulse width tsckl(6) 1/2 tsck high level pulse width tsckh(6) 1/2 tsckha(6a) ? continuous data transmission/ reception mode of sio0 is not in use simultaneous. ? cmos output selected. ? see fig. 6. tsckh(6) + (5/3)tcyc tsckh(6) + (10/3)tcyc tcyc tsckha(6b) ? continuous data transmission/ reception mode of sio0 is in use simultaneous. ? cmos output selected. ? see fig. 6. tsckh(6) + (5/3)tcyc tsckh(6) + (19/3)tcyc serial input data setup time tsdi(3) si2(si2p1), sb2(si2p1) ? must be specified with respect to rising edge of sioclk ? see fig. 6. 2.2 to 5.5 0.03 s data hold time thdi(3) 0.03 serial output output delay time tdd0(5) so2 (si2p0), sb2(si2p1) ? must be specified with respect to falling edge of sioclk ? must be specified as the time to the beginning of output state change in open drain output mode. ? see fig. 6. 2.2 to 5.5 (1/3)tcyc +0.05 note 4-3-1: these specifications are theoretical values. add margin depending on its use. note 4-3-2: to use serial-clock-input , a time from si2run being set when serial clock is "h" to the first negative edge of the serial clock must be longer than tsckha.
lc87f5dc8a no.a0143-20/28 pulse input conditions at ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit high/low level pulse width tpih(1) tpil(1) int0(p70), int1(p71), int2(p72), int4(p20 to p23), int5(p24 to p27), int6(p20), int7(p24) ? interrupt source flag can be set. ? event inputs for timer 0 or 1 are enabled. 2.2 to 5.5 1 tcyc tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 2 tpih(3) tpil(3) int3(p73) (the noise rejection clock is selected to 1/32.) ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 64 tpih(4) tpil(4) int3(p73) (the noise rejection clock is selected to 1/128.) ? interrupt source flag can be set. ? event inputs for timer 0 are enabled. 2.2 to 5.5 256 tpil(5) res reset acceptable. 2.2 to 5.5 200 s ad converter characteristics at ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit resolution n an0(p80) to an7(p87), an8(p70), an9(p71), an10(xt1), an11(xt2) , an12(pa3), an13(pa4), an14(pa5) 3.0 to 5.5 8 bit absolute precision et (note 6-1) 3.0 to 5.5 1.5 lsb conversion time tcad ad conversion time=32 tcyc (when adcr2=0) (note 6-2) 4.5 to 5.5 11.74 (tcyc= 0.367 s) 97.92 (tcyc= 3.06 s) s 3.0 to 5.5 31.36 (tcyc= 0.980 s) 97.92 (tcyc= 3.06 s) ad conversion time=64 tcyc (when adcr2=1) (note 6-2) 4.5 to 5.5 15.68 (tcyc= 0.245 s) 97.92 (tcyc= 1.53 s) 3.0 to 5.5 31.36 (tcyc= 0.490 s) 97.92 (tcyc= 1.53 s) analog input voltage range vain 3.0 to 5.5 v ss v dd v analog port input current iainh vain=v dd 3.0 to 5.5 1 a iainl vain=v ss 3.0 to 5.5 -1 note 6-1: the quantization error ( 1/2lsb) is excluded from th e absolute accuracy value. note 6-2: the conversion time refers to the interval from th e time the instruction for starting the converter is issued till the complete digital value corresponding to the analog input value is loaded in the required register.
lc87f5dc8a no.a0143-21/28 consumption current characteristics at ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit normal mode consumption current (note 7-1) iddop(1) vdd1 =vdd2 =vdd3 ? fmcf=12mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 4.5 to 5.5 9.5 22 ma iddop(2) 2.8 to 4.5 5.5 15 iddop(3) ? fmcf=8mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 4.5 to 5.5 7 16.5 iddop(4) 2.5 to 4.5 4 12 iddop(5) ? fmcf=4mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 4.5 to 5.5 2.8 6.5 iddop(6) 2.2 to 4.5 1.5 4.5 iddop(7) ? fmcf=0hz(osc illation stopped) ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped ?1/2 frequency division ratio. 4.5 to 5.5 1 4.5 iddop(8) 2.2 to 4.5 0.55 3.5 iddop(9) ? fmcf=0hz(osc illation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? system clock set to 1mhz with frequency variable rc oscillation ? internal rc oscillation stopped ? 1/2 frequency division ratio. 4.5 to 5.5 1.3 5.5 iddop(10) 2.2 to 4.5 0.7 4.5 iddop(11) ? fmcf=0hz(osc illation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? system clock set to 32.768khz side. ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 4.5 to 5.5 40 120 a iddop(12) 2.2 to 4.5 20 80 note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page.
lc87f5dc8a no.a0143-22/28 continued from preceding page. parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit halt mode consumption current (note 7-1) iddhalt(1) v dd 1 =v dd 2 =v dd 3 ? halt mode ? fmcf=12mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 12mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 4.5 to 5.5 3.8 8.2 ma iddhalt(2) 2.8 to 5.5 2.2 4.4 iddhalt(3) ? halt mode ? fmcf=8mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 8mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/1 frequency division ratio. 4.5 to 5.5 2.8 5.9 iddhalt(4) 2.5 to 5.5 1.5 3.0 iddhalt(5) ? halt mode ? fmcf=4mhz ceramic oscillation mode ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to 4mhz side ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 4.5 to 5.5 1.2 2.7 iddhalt(6) 2.2 to 4.5 0.6 1.5 iddhalt(7) ? halt mode ? fmcf=0hz(osc illation stopped) ? fmx?tal=32.768khz by crystal oscillation mode ? system clock set to internal rc oscillation ? frequency variable rc oscillation stopped ?1/2 frequency division ratio. 4.5 to 5.5 0.4 1.1 iddhalt(8) 2.2 to 4.5 0.2 0.8 iddhalt(9) ? halt mode ? fmcf=0hz(osc illation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? system clock set to 1mhz with frequency variable rc oscillation ? internal rc oscillation stopped ? 1/2 frequency division ratio. 4.5 to 5.5 1.2 4 iddhalt(10) 2.2 to 4.5 0.6 3 iddhalt(11) ? halt mode ? fmcf=0hz(osc illation stopped) ? fmx'al=32.768khz by crystal oscillation mode. ? system clock set to 32.768khz side. ? internal rc oscillation stopped ? frequency variable rc oscillation stopped ? 1/2 frequency division ratio. 4.5 to 5.5 20 70 a iddhalt(12) 2.2 to 4.5 10 50 note 7-1: the consumption current value includes none of the cu rrents that flow into the output tr and internal pull-up resistors. continued on next page.
lc87f5dc8a no.a0143-23/28 continued from preceding page. parameter symbol pin/ remarks conditions specification v dd [v] min typ max unit current drain during hold mode iddhold(1) v dd 1 ? hold mode ? cf1=vdd or open (external clock mode) 4.5 to 5.5 0.04 10 a iddhold(2) 2.2 to 4.5 0.02 5 current drain during time-base clock hold mode iddhold(3) v dd 1 ? timer hold mode ? cf1=vdd or open (external clock mode) ? fmx'tal=32.768khz by crystal oscillation mode 4.5 to 5.5 18 60 iddhold(4) 2.2 to 4.5 6 40 f-rom programming characteristics at ta = +10c to +55c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit onboard programming current iddfw(1) v dd 1 ? 128-byte programming ? erasing current including 3.0 to 5.5 25 40 ma programming time tfw(1) ? 128-byte programming ? erasing current including ? time for setting up 128 byte data is excluded. 3.0 to 5.5 22.5 45 ms uart (full duplex) op erating conditions at ta = -20c to +70c, v ss 1 = v ss 2 = v ss 3 = 0v parameter symbol pin/remarks conditions specification v dd [v] min typ max unit clock rate ubr,ubr2 utx1(p32), rtx1(p33), utx2(p22), rtx2(p23) 2.2 to 5.5 16/3 8192/3 tcyc data length: 7/8/9 bits (lsb first) stop bits: 1-bit(2-bit in continuous data transmission) parity bits: none *example of continuous 8-bit data transmission mode processing (first transmit data=55h) *example of continuous 8-bit data reception mode processing (first receive data=55h) transmit data (lsb first) start of transmission end of transmission ubr, ubr2 start bit stop bit ubr, ubr2 receive data (lsb first) start of reception end of reception start bit stop bit
lc87f5dc8a no.a0143-24/28 v dd 1, v ss 1 terminal condition it is necessary to place capacitors between v dd 1 and v ss 1 as describe below. ? place capacitors as close to v dd 1 and v ss 1 as possible. ? place capacitors so that the length of each terminal to th e each leg of the capacitor be equal (l1 = l1?, l2 = l2?). ? place high capacitance capacitor c1 and lo w capacitance capacitor c2 in parallel. ? capacitance of c2 must be more than 0.1 f. ? use thicker pattern for v dd 1 and v ss 1. v dd 3, v ss 3 terminal condition it is necessary to place capacitors between v dd 3 and vss3 as describe below. ? place capacitors as close to v dd 3 and v ss 3 as possible. ? place capacitors so that the length of each terminal to the each leg of the capac itor be equal (l3 = l3?). ? capacitance of c3 must be more than 0.1 f. ? use thicker pattern for v dd 3 and v dd 3. v ss 1 v dd 1 l1? l2? l1 l2 c1 c2 v ss 3 v dd 3 l3? l3 c3
lc87f5dc8a no.a0143-25/28 characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main system clock oscillation circuit that are measured using a our designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c1 [pf] c2 [pf] rf1 [ ] rd1 [ ] typ [ms] max [ms] 12mhz murata cstce12m0g52-r0 (10) (10) open 470 2.8v to 5.5v 0.05 0.15 internal c1,c2 8mhz cstce8m00g52-r0 (10) (10) open 2.2k 2.7v to 5.5v 0.05 0.15 internal c1,c2 cstls8m00g53-b0 (15) (15) open 680 2.5v to 5.5v 0.05 0.15 internal c1,c2 4mhz cstcr4m00g53-r0 (15) (15) open 3.3k 2.2v to 5.5v 0.05 0.15 internal c1,c2 cstls4m00g53-r0 (15) (15) open 3.3k 2.2v to 5.5v 0.05 0.15 internal c1,c2 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after v dd goes above the operating voltage lower limit (see figure 4). characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a our designated oscillation characteristics evaluation board and exte rnal components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator nominal frequency vendor name oscillator name circuit constant operating voltage range [v] oscillation stabilization time remarks c3 [pf] c4 [pf] rf [ ] rd2 [ ] typ [s] max [s] 32.768khz seiko epson mc-306 18 18 open 560k 2.2 to 5.5 1.3 3.0 applicable cl value = 12.5pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit is ex ecuted and to the time interval that is required for the oscillation to get stabilized after the hold mode is reset (see figure 4). note : the components that are involved in oscillation should be placed as close to the ic and to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 ceramic oscillation circuit figure 2 crystal oscillation circuit figure 3 ac timing point 0.5v dd c3 rd2 c4 x?tal xt2 xt1 rf2 c1 c2 cf cf2 cf1 rd1 rf1
lc87f5dc8a no.a0143-26/28 reset time and oscillation stabilizing time hold reset signal and oscillation stabilizating time figure 4 oscillation stabilizating times v dd limit power supply res internal rc oscillation cf1, cf2 xt1, xt2 operating mode reset time tmscf tmsx?tal unfixed reset instruction execution v dd gnd internal rc oscillation cf1, cf2 xt1, xt2 operation mode hold release signal hold release signal valid tmscf tmsx?tal hold halt
lc87f5dc8a no.a0143-27/28 figure 5 reset circuit figure 6 serial input/output test condition figure 7 pulse input timing condition c res v dd r res res note : select c res and r res value to assure that at least 200s reset time is generated after the v dd becomes higher than the minimum operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckla tsckha thdi tsdi tddo data ram transmission period (only sio0,2) data ram transmission period (only sio0,2)
lc87f5dc8a no.a0143-28/28 ps on semiconductor and the on logo are registered trademarks of semiconductor components industries, llc (scillc). scillc owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. a listing of scillc?s product/patent coverage may be accessed at www.onsemi.com/site/pdf/patent-marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc mak es no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability ar ising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequentia l or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s techn ical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorize d for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other appli cation in which the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of persona l injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture o fthe part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws a nd is not for resale in any manner.

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